FEX, an x86 emulator, has published a detailed technical analysis of the core performance challenges in emulating x86 processors on ARM-based systems. According to the article, the fundamental issue stems from a mismatch between x86’s Total Store Ordering (x86-TSO) memory model and ARM’s weaker memory consistency model.
The x86-TSO model enforces strict memory coherency, ensuring that when a processor writes to memory, that change becomes immediately visible to all other processors in the system. This matches programmer expectations and provides strong consistency guarantees. In contrast, ARM’s weak memory model prioritizes efficiency and power consumption by allowing memory stores to remain invisible to other processors initially, avoiding the hardware costs of cache invalidation and snooping.
To bridge this gap, FEX converts all x86 memory loads into ARM load-acquire instructions and x86 stores into store-release instructions. This approach guarantees the same memory semantics as x86, though it is more restrictive than necessary. According to the article, this solution comes at a steep performance cost. Microbenchmarks reveal significant performance penalties across multiple ARM processors when using acquire-load instructions, with the AmpereOne CPU experiencing particularly severe degradation.
The performance hit occurs because acquire-release instructions were not designed for the high-frequency use case that x86 emulation demands. When these instructions execute in the millions per second, ARM CPUs cannot reorder load instructions around each other, constraining optimization opportunities.
FEX identifies a potential path forward through the LRCPC (Load-Acquire RCpc) instruction extension, mandatory since ARMv8.3. This extension introduces a new “Release Consistency processor consistent” memory model specifically designed for x86 emulation requirements. According to the article, LRCPC-load instructions achieve performance nearly matching regular load performance across most tested platforms, offering a more efficient solution to the emulation challenge.
The article examines additional complications beyond basic memory ordering, including atomic instructions, split-lock handling, and uncached memory requirements, framing memory model emulation as a pervasive challenge affecting every emulated x86 application.
Key facts
- FEX emulator faces critical performance challenges emulating x86’s strict Total Store Ordering (TSO) memory model on ARM’s weak memory model
- The current workaround uses load-acquire and store-release instructions for every memory access, causing significant performance penalties on some ARM CPUs
- Newer ARM LRCPC instructions (mandatory since ARMv8.3) provide better performance for x86 emulation by matching regular load instruction speeds