Ternary large language models (LLMs) store each weight as one of three values –1, 0, or +1. Because there are three equiprobable symbols, the information‑theoretic lower bound is log₂3 ≈ 1.585 bits per weight. In practice, many implementations pack five ternary weights into a single byte, which translates to 1.625 bits per weight after rounding to power‑of‑two group sizes. This conventional approach treats the three symbols as equally likely, ignoring any skew in their actual distribution. In a study submitted to arXiv on 14 September 2026, Evangelos Georganas and co‑authors examined the weight statistics of 29 publicly available ternary LLM checkpoints. They found that the proportion of zero weights varies widely, reaching as high as 51.5 % in some models. This observation motivated the design of a new layout called BITCOS (Bitmap‑Informed Ternary COmpression Scheme). BITCOS consists of two parts: a dense presence bitmap that marks which positions are non‑zero, and a compacted sign vector that stores only the +1 or –1 values for those positions. For a given zero density z (the fraction of weights equal to zero), the scheme requires 2 − z bits per weight element. When z is 0.5, the cost drops to 1.5 bits per weight; for the sparsest model in the set, where zeros exceed 51.5 %, the measured cost falls to approximately 1.485 bits per weight, which is below both the equiprobable bound and the five‑trit packing baseline. The authors report that BITCOS outperforms the conventional five‑trit packing in 26 out of the 29 tested models, yielding storage savings ranging from a few tenths of a bit to roughly 0.14 bits per weight. Beyond storage, the layout is designed for efficient unpacking on contemporary hardware. The paper provides optimized instruction sequences for AVX‑512, AVX2, and Intel Xe2 GPUs, demonstrating that the decompression overhead is negligible. When plugged into production‑grade ternary matrix‑vector multiplication kernels, the combined effect of reduced memory traffic and fast unpacking yields up to a 1.28× speed‑up at the zero densities observed in real‑world models. End‑to‑end inference benchmarks were run on five platforms—client‑grade CPUs, server‑grade CPUs, integrated Xe2 graphics, and discrete Xe2 GPUs. Across these systems, decode throughput improved by as much as 1.18× on CPUs and 1.27× on GPUs relative to the baseline five‑trit packing implementation. The results suggest that adapting storage to the actual sparsity of ternary weights can deliver measurable gains in both memory footprint and inference latency without altering the underlying model architecture or training procedure.
