OpenAI unveiled Jalapeño, its debut AI accelerator chip, on August 25. The chip delivers up to 13.4 petaflops of 4-bit compute and can reduce end-to-end latency by up to 3.6 times compared to Nvidia’s GB300, while consuming less power, according to OpenAI’s benchmarks.
The design process itself exemplifies how large language models can accelerate hardware development. Jalapeño moved from first architecture concept to first silicon in under 20 months, with only nine months separating the initial RTL (register-transfer level code) from tape-out, when the finished design goes to manufacturing.
Richard Ho, vice president of hardware at OpenAI, said that “the models are giving superpowers to our engineers,” while emphasizing that engineers remained in control. “Our engineers are still driving the work. They’re still the final arbiter of what’s going on. But they can do things a lot faster.” The design team averaged fewer than 100 people throughout the project.
OpenAI partnered with Broadcom on implementation, with OpenAI handling end-to-end system design including the inference accelerator, memory hierarchy, and networking, while Broadcom managed physical design from the gates onward.
The team leveraged OpenAI’s LLMs within a workflow built around Accelerated Hardware Synthesis (XLS), an open-source tool originally developed at Google. XLS allows engineers to write in programming languages like DSLX and C++, which the tool converts to Verilog, a hardware description language. According to Chris Leary, a member of technical staff at OpenAI, LLMs proved “much better at software-looking things,” making them well-suited for high-level synthesis tasks.
When first chips returned from the foundry in May, OpenAI’s internal AI models optimized software for benchmarks. On DeepSeek’s multi-head latent attention kernel benchmark, performance improved from 0.31 percent of theoretical ceiling to 88.94 percent in roughly 40 hours. Ho noted this result is repeatable, potentially reducing time between chip delivery and production ramps.
During the project, the team gained access to more advanced models, including precursors to GPT-6 Astra, which can work directly in Verilog without XLS’s translation layer. Ho confirmed the team used internal LLMs fine-tuned specifically for chip design that are not publicly available. He declined to detail which models were used but stated that lessons from Jalapeño will be incorporated into commercial LLMs, saying “Astra and following models will be very good at chip design.”
Key facts
- Jalapeño delivers up to 13.4 petaflops of 4-bit compute with 232 gigabytes of advanced memory
- The chip can reduce end-to-end latency by up to 3.6 times compared to Nvidia’s GB300
- Design timeline: first architecture concept to first silicon in under 20 months; RTL to tape-out in nine months
- OpenAI’s design team averaged fewer than 100 people including system design, software, and supply chain roles
- OpenAI partnered with Broadcom, which handled physical design while OpenAI managed system architecture and design
- LLMs were used to accelerate high-level synthesis and software optimization tasks
- On a benchmark test, AI-optimized software improved performance from 0.31% to 88.94% of theoretical ceiling in 40 hours
- The Jalapeño team had access to internal LLMs fine-tuned for chip design not available to the public